Cap Dump Circuit using High-Sided Switching

[JulesP]

Sorry I will upload a bigger one tomorrow

[JulesP]

Hi Gary,

Having looked more carefully at the spec sheet I can see that Vgs threshold is between -1 and -3V so the Q2 Gate must be at least say 3V lower than the Source V to fully switch the FET on.

With the Zener installed the Q2 Gate will be at a max of 15V which will surely keep the P channel FET on all the time as the Gate will always be more than Vgs (thres) below the Source, certainly while the Source is between 24 and 18V. So it will almost never switch off. Surely we need the Gate to return to the same as the Source (24V) to be able to turn the FET off?

To put it another way, Vgs must be 0V for the FET to be fully off and at least -3V to turn on.

Maybe I’m confusing the voltages before the dump with during, but when the optoisolator is off (and Q1) then we need Vg to be the same as Vs (Vgs = 0V) so that Q2 if off. If a Zener is holding Vg at 15V max all the time then Vgs will be -2-9V and so Q2 will be on even when the optoisolator and Q1 are off?

I’ve attached the whole spec sheet rather than a phone screen grab and the gate threshold values are on page 2.

Jules


Si3421DV.pdf

[Gary Hammond]

Hi Julian,

To put it another way, Vgs must be 0V for the FET to be fully off and at least -3V to turn on.

That is correct.

So it will almost never switch off.

NO, that is incorrect.

If a Zener is holding Vg at 15V max all the time then Vgs will be -2-9V and so Q2 will be on even when the optoisolator and Q1 are off?

No, that is incorrect. Those voltages (-9 to -2) are what is between the Q2 gate and ground, which is unimportant and dropping in value during cap discharge. We are only concerned with the voltage between the gate and source.

All the time the Q1 transistor is turned on, it's collector it is at 15 volts below the source because of current flow thru the zener, i.e. V_gs. When the opto turns off it also turns off Q1 shutting off any current flow thru both the zener and R13. This results in the Q1 collector and Q2 gate to switch back to the same value as the source making V_sg = 0, which in turn shuts off any current flow through Q2.

when the optoisolator is off (and Q1) then we need Vg to be the same as Vs (Vgs = 0V) so that Q2 if off.

That is correct, and is what happens when the opto shuts Q1 off.

Having looked more carefully at the spec sheet I can see that Vgs threshold is between -1 and -3V so the Q2 Gate must be at least say 3V lower than the Source V to fully switch the FET on.

That's correct. But in looking at the spec sheet, I doubt that the Si3421DV is robust enough to do the job. It is only rated at max continuous current of 8 amps and max pulse current of 50 amps. And it's max V_ds is only 30 volts. While the voltage rating is marginal at best, the current rating is way too small. Cap dump pulses can easily exceed 100 amps or more. This would apply to all three FETs in the circuit, Q2, Q5, and Q6.

In my cap dump I use four, in parallel, IRFP4310ZPbF N-channel FETs rated at 100 V_ds , 134 max continuous amps, and 560 max pulse amp. This discharges thru a large AWS#4 battery cable between the caps and the battery. If you hold a ceramic magnet next to this cable, you can feel it jump in your hand with each discharge of the cap dump! Here's a picture of it for your reference.


Gary Hammond,

[JulesP]

Hi Gary, Ok I get the logic of what’s happening now.

Regarding the FETs I need to find a P channel one that is suitably robust. Meanwhile I’m drawing up the schematic in a leisurely pace.

Jules

[JulesP]

Hi Gary,

Here is a schematic for the cap dump circuit and I have one query:

While the large external capacitor is charging up with the HV pulses, I wondered if it was prudent to include a 12V supply (Connector H2 from the mainboard) so that the comparator etc can operate without waiting for its supply? If so it should not interfere with the discharging of pulses to the batteries.

I have suggested the SQP90P06 P FET with its higher continuous Ids of 120A and pulse 480A. With this, my more important issue will be creating thick enough tracks on a PCB to allow for high pulse currents. I will need to enquire if the surface PCB coating will melt off with a soldering iron to allow extra solder thickening or if I need to ensure that certain tracks don't have a protective coating.

Regards,

Jules

[Gary Hammond]

Hi Julian,

While the large external capacitor is charging up with the HV pulses, I wondered if it was prudent to include a 12V supply (Connector H2 from the mainboard) so that the comparator etc can operate without waiting for its supply? If so it should not interfere with the discharging of pulses to the batteries.

No. The cap will fill up very quickly to 24 volts on it's own and then discharge to approximately 17 volts each dump. This should occur 2 or 3 times per second and will never go down to the value of the 12 volt power supply. The addition of a 12 volt power supply would be totally ineffective.

I see you have redrawn the biasing of Q1 and Q2 completely different from what I showed you in the last schematic I posted. Was this in error, or did you intend to change it?

I have suggested the SQP90P06 P FET with its higher continuous Ids of 120A and pulse 480A. With this, my more important issue will be creating thick enough tracks on a PCB to allow for high pulse currents. I will need to enquire if the surface PCB coating will melt off with a soldering iron to allow extra solder thickening or if I need to ensure that certain tracks don't have a protective coating.

I doubt that board traces can be made large enough to handle the large current pulses. I would suggest hard wiring this part of the circuit similar to what is shown in the photo of mine. I would go no smaller than AWG#10 for these high pulse current paths.

Gary Hammond,

[JulesP]

Hi Gary,

I hadn’t intended to change anything although the annotations have changed due to the schematic software.

Q1and 2 are now Q3 and 1 and I will check again tomorrow but I thought I had it the same (albeit not always in the same relative positions).

I can see how to use heavy gauge wire outside of the circuit but how would I connect the diodes D2 and 4 for example to a 10awg length of wire without using some form of connectors along its length?

Julian

[JulesP]

Hi Gary,

I have been through my circuit and can't find anything different from the one drawn in Keynote, apart from one resistor (R10) not being changed from 100k to 220R.

To illustrate, I have coloured the biasing around Q1 in blue and done similarly on the schematic around the same BJT (Q3). The components, their values and connections are the same. Similarly, I have shown the FET Q2 in purple and on the schematic (Q1).

If you can see something I can't then please be specific and let me know.

Thanks

Jules

[Gary Hammond]

Hi Jules,

I have been through my circuit and can't find anything different from the one drawn in Keynote, apart from one resistor (R10) not being changed from 100k to 220R.

That is one of the changes I referred to. The other change you made is noted in the following sentences.

The top pic in your last post (#23) is different than the ones I showed in post #11 (without the zener) and post #13 with the zener added.

You have added back in a 10K resistor between the gate of Q2 in the top pic that I had deleted. This makes it in parallel with the 2k2 resistor and the zener, which will slightly increase the current thru the TIP41C transistor when it turns on, and is not needed. Go back and look at posts #11 and #13 again.

I can see how to use heavy gauge wire outside of the circuit but how would I connect the diodes D2 and 4 for example to a 10awg length of wire without using some form of connectors along its length?

You could use bare copper wire and solder jumpers to it. Or you could use insulated wire and just strip a couple of small places to solder the jumpers on. Or you could use connectors, but this would also add unwanted resistance in the high current discharge path.

I used a flattened piece of copper tubing soldered to all the capture cap terminals. All the other wiring was soldered to these strips with small jumper wires going to the printed circuit board. Look closely at the photo I included in post #18. I also mounted all the FETs on a heat sink with all the source and drain leads installed in connectors which were soldered to the flattened copper tubing as well. The resistance in the high current dump path needs to be kept as low as possible!

Gary Hammond,

[JulesP]

Gary, I will have another look based on your description. I see the 10k one you mean but that is there to pull up the gate when it switches off, like I have for the other FETs. I guess it’s not needed and confuses things. I didn't update my Keynote drawing after you had removed it.

Got a little time to tinker so have changed op-amp to a more modern faster one (LM319MX), giving it a separate supply and ground to avoid noise from the cap supply and am thinking of encouraging the base of Q3 to switch off faster and cleaner with a 1k resistor to Ground?

Here it is tidied up somewhat:




Thanks

Jules

[Gary Hammond]

Hi Jules,

giving it a separate supply and ground to avoid noise from the cap supply and am thinking of encouraging the base of Q3 to switch off faster and cleaner with a 1k resistor to Ground?

You can do either or both of those things, but I'm not sure either would be helpful. And if you use an added 12 volt supply, I don't think the 15 volt D5 zener would even conduct and could be eliminated altogether.

Gary Hammond,

[JulesP]

Noted Gary,

It turns out the TS302 is not a push-pull comparator after all so I have modified it to a TS3702 which is more like the LM741 but performs better.

So here is the 'final' schematic. (I'm wary of saying that word)

You may have noticed the 'Rotor in' connector at the top left in addition to some Test Points (easier to get scope probes attached to). This is for the input of the rotor energy that I think would be ideal to deliver to the batteries via the cap dump circuit rather than directly.

As it's a different, but related topic, I thought I would start a new thread for it soon and share my design proposals and invite comments.

Jules

[JulesP]

Hi Gary,


I have been preparing the PCB for the Cap Dump circuit (see attached) but have had a niggling feeling about the biasing of the two TIP41C transistors that feed the gates of Q5&6. These gates are fed from my mainboard and taken off the gate feeds of the two battery swapper FETs as part of the mechanism to feed the cap pulses to the right battery. I reason that the biasing requirements will be different for the TIP41Cs.

To try and see if I need to adjust the resistor network around the TIP41Cs (Q2&4 on the cap dump circuit) I have drawn what I think is the equivalent circuit and shown it with the schematic in the attached.

Would you mind taking a look at this and seeing if the figures work or how I should adjust or add some resistors to avoid melting Q2&4?

Perhaps instead I should replace the TIP41Cs with some FETs, like the ones used in the swap circuit, that might get round the issue?

Hoping you are well in this new year.

Regards,

Julian

[JulesP]

Here is my suggestion for using FETs instead of the TIP41Cs. I have written the switching logic in some text on the schematic:

[JulesP]

However, given that Q5&6 are P channel FETs my previous suggestion using FETs may be the wrong way round?